Method of selecting metrics and receiver using the same

ABSTRACT

A method and apparatus of selecting N metrics among M metrics is provided. The apparatus determines M metrics P(i), where i=1, . . . , M. Each P(i) is represented by B bits. The apparatus determines N metrics among M metrics. The complexity for configuring the circuit is decreased, and the length of the critical path is reduced.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority of Korean PatentApplication No. 10-2011-0047274 filed on May 19, 2011, all of which isincorporated by reference in its entirety herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to data processing, and more particularly,to a method and apparatus of selecting N metrics among M metrics.

2. Related Art

A wireless communication system has been prevalently developed in orderto provide various kinds of communication services such as audio, data,or the like. Generally, the wireless communication system is a multipleaccess system that may share available system resources (bandwidth,transmission power, or the like) to support communication withmulti-user. Examples of a multiple access system may include a codedivision multiple access (CDMA) system, a frequency division multipleaccess (FDMA) system, a time division multiple access (TDMA) system, anorthogonal frequency division multiple access (OFDMA) system, a singlecarrier frequency division multiple access (SC-FDMA) system, or thelike.

Multiple input multiple output (MIMO) is a technology that has beeninterested due to characteristics that a throughput increases withoutallocating additional resources. Channel capacity of the MIMO systemmainly depends on a detection method used in a receiver in order torestore a received signal. Therefore, a detection method implementingboth of high performance and low complexity has been interested.

Maximum likelihood (ML) detection has been known as a MIMO detectionmethod that may obtain most ideal performance by searching all signalvectors in order to restore a modulated signal. However, the MLdetection has a problem that complexity exponentially increases as thenumber of transmit antennas increases.

QR-decomposition with M-algorithm (QRD-M) is one of methods developed asan alternative to the ML detection having high complexity. A mobileterminal uses limited power and is vulnerable to latency. Therefore, itis difficult to use a detection method having a high deviation andarbitrarily changed complexity. The QRD-M trades off between bit errorrate (BER) performance and complexity to have fixed complexity andexcellent BER performance.

The QRD-M has a tree-search structure having a trade-off betweenperformance and a calculation amount according to a size of M, which isthe number of survivor paths. However, since a large M value includingaccurate paths in all steps should be used in order to approachperformance of the ML detection, a large calculation amount is required.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus of calculating Nminimum values by sequentially searching the most significant bit (MSB)to the least significant bit (LSB) from M metrics.

In an aspect, a method of selecting N metrics among M metrics, whereM>N≧1, is provided. The method includes determining M metricsP(i)=[b_(i)(B−1) . . . b_(i)(1) b_(i)(0)], where i=1, . . . , M, eachP(i) being represented by B bits, initializing two comparison values,P(i)⁰ and P(i)¹, to zero for each P(i), determining a sum of j-th bitfor M P(i)s, where j=0, 1, . . . , B−1, as shown:

${{sum}(j)} = {{{\sum\limits_{i = 1}^{M}\left( {\sim{P(i)}^{0}} \right)}\&}\mspace{14mu} \left( {P(i)}^{1} \middle| {b_{i}(j)} \right)}$

where sum(j) denotes the sum of j-th bit for M P(i)s, ‘˜’ denotes a bitinversion operation, ‘&’ denotes a bit AND operation, and ‘|’ denotes abit OR operation, updating P(i)⁰ and P(i)¹ for each P(i) by comparingsum(j) and (M−N), and selecting at least one P(i) having a P(i)⁰ valueof 1 among M P(i)s.

The method may further include selecting at least one P(i) having aP(i)⁰ value of 1 and a P(i)¹ value of 0 when the number of selected P(i)is smaller than N.

The step of updating P(i)⁰ and P(i)¹ for each P(i) may include updatingP(i)⁰ to 1 with respect to i in which)(˜P(i)⁰)&(P(i)¹|b_(i)(j))=0 whensum(j) is larger than (M−N).

The step of updating P(i)⁰ and P(i)¹ for each P(i) may include updatingP(i)¹ to 1 with respect to i in which (˜P(i)⁰)&(P(i)¹|b_(i)(j))=1 whensum(j) is smaller than (M−N).

The step of updating P(i)⁰ and P(i)¹ for each P(i) may include whensum(j) is the same as (M−N), updating P(i)⁰ to 1 with respect to i inwhich (˜P(i)⁰)&(P(i)¹|b_(i)(j))=0 and updating P(i)¹ to 1 with respectto i in which (˜P(i)⁰)&(P(i)¹|b_(i)(j))=1.

In another aspect, a method of receiving data is provided. The methodincludes receiving a receive signal from a transmitter, determining Mmetrics P(i)=[b_(i)(B−1) . . . b_(i)(1) b_(i)(0)], where i=1, . . . , M,based on a channel on which the receive signal is received, each P(i)being represented by B bits, determining N metrics among the M P(i)s,where M>N≧1, and restoring a transmit signal transmitted by thetransmitter from the receive signal based on the N metrics.

In still another aspect, a receiver includes a receive circuitconfigured for receiving a receive signal from a transmitter, a metricdetermining unit configured for determining M metrics P(i)=[b_(i)(B−1) .. . b_(i)(1) b_(i)(0)], where i=1, . . . , M, based on a channel onwhich the receive signal is received, each P(i) being represented by Bbits, and determining N metrics among the M P(i)s, where M>N≧1, and arestoring unit configured for restoring a transmit signal transmitted bythe transmitter from the receive signal based on the N metrics.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a Merge-Sort process of calculating 3 metrics among 8metrics.

FIG. 2 shows Merge-Sort 4, 8, and 16 values.

FIG. 3 shows a logic calculating 64 minimum values among 256 distancevalues.

FIG. 4 shows a process of calculating 1 minimum value among 8 distancevalues of 4 bits.

FIG. 5 shows a process of calculating 3 minimum values among 8 distancevalues of 4 bits according to an exemplary embodiment of the presentinvention.

FIG. 6 is a circuit diagram showing a process of calculating 3 minimumvalues among 8 distance values of 4 bits.

FIG. 7 shows a method of sorting selected minimum values.

FIG. 8 shows a method of re-sorting 3 minimum values selected among 16values.

FIG. 9 is a circuit diagram showing a method of calculating a minimumvalue among 8 distance values of 4 bits.

FIG. 10 show a process of calculating a minimum value among 8 distancevalues of 4 bits.

FIG. 11 shows 32 1-bit additions.

FIG. 12 is a block diagram showing a receiver implementing a suggestedembodiment.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

QR-decomposition with M-algorithm (QRD-M) is a method based on atree-search algorithm. The tree-search algorithm selects M pathsdetermined to have high reliability among path metrics extended in eachstep and does not consider remaining paths.

In order to describe general QRD-M, a MIMO system including T transmitantennas and L receive antennas is considered.

A receive signal vector y is represented as follows:

y=Hs+n  [Equation 2]

where s means a transmit signal vector, H means a channel matrix havinga T×L size, and n means a noise vector. A component h_(ij) of the i-throw and j-th column of H indicates a channel gain between the j-thtransmit antenna and the i-th receive antenna.

QR decomposition is performed on the channel matrix H to obtain a normalorthogonal matrix Q having a L×L size and an upper triangular matrix Rhaving a T×T size as follows.

H=QR  [Equation 2]

Let a conjugate transpose matrix of Q be Q^(H). Q^(H)Q=I. Here, I meansan identity matrix.

Both sides of Equation 1 are multiplied by Q^(H) to obtain the followingEquation:

{tilde over (y)}=Rs+ñ  [Equation 3]

where {tilde over (y)}=Q^(H)y and ñ=Q^(H)n.

A receive vector of Equation 3 is divided for each row to obtain thefollowing Equation:

$\begin{matrix}\begin{matrix}{{\overset{\sim}{y}}_{1} =} & {{R_{1,1}s_{1}} + {R_{1,2}s_{2}} + {R_{1,3}s_{3}} + \ldots + {R_{1,T}s_{T}} + {\overset{\sim}{n}}_{1}} \\{{\overset{\sim}{y}}_{2} =} & {{R_{2,2}s_{2}} + {R_{2,3}s_{3}} + \ldots + {R_{2,T}s_{T}} + {\overset{\sim}{n}}_{2}} \\\vdots & \; \\{{\overset{\sim}{y}}_{T - 1} =} & {{R_{{T - 1},{T - 1}}s_{T - 1}} + {R_{{T - 1},T}s_{T}} + {\overset{\sim}{n}}_{T - 1}} \\{{\overset{\sim}{y}}_{T} =} & {{R_{T,T}s_{T}} + {\overset{\sim}{n}}_{T}}\end{matrix} & \left\lbrack {{Equation}\mspace{14mu} 4} \right\rbrack\end{matrix}$

where s_(k) means the k-th component of a transmit vector s, R_(j,k)means the j,k-th component of the upper triangular matrix R.

From Equation 4, it may be appreciated that it is most effective toperform estimation from the T-th transmit signal s_(T) when there is nointerference of other transmit signals.

First, a path metric in a detection step, that is, a step of estimatingthe T-th transmit signal s_(T) may be calculated as follows:

∥{tilde over (y)} _(T) −R _(T,T) {tilde over (s)} _(T,l)∥²  [Equation 5]

where {tilde over (s)}_(T,l) indicates the l-th candidate symbol ofs_(T).

Only N candidate paths in which the Euclidean distance value becomesminimum are selected, and remaining paths are deleted.

Next, the Euclidean distance value accumulated from the i-th detectionstep (T−i+1-th row of R) to the n-th detection step is represented bythe following Equation:

$\begin{matrix}{\sum\limits_{j = 1}^{i}{{{\overset{\sim}{y}}_{T - j + 1} - {\sum\limits_{k = {T - j + 1}}^{T}{R_{{T - j + 1},k}{{\overset{\sim}{s}}_{k,l}(n)}}}}}^{2}} & \left\lbrack {{Equation}\mspace{14mu} 6} \right\rbrack\end{matrix}$

where {tilde over (s)}_(k,l)(n) indicates the l-th candidate symbol ofs_(k) of the n-th path.

In order to assist the understanding, a QRD-M method may be described asfollows.

(1) QR decomposes a channel matrix H.

(2) Multiply a receive signal vector y by Q^(H) to form a format ofEquation 3.

(3) Extend each of all paths to C nodes which are the number ofcandidate symbols.

(4) Calculate M path metric values using Equation 6.

(5) Select N survival paths having a minimum value after sorting the Mpath metric values in an ascending order.

(6) Return step (3) to repeat up to a final detection step.

(7) In a final detection step, select one path having a minimum valueamong path metrics accumulated up to now to estimate the selected pathas a transmit signal.

A process of calculating a path metric among the above-mentionedprocesses occupies the largest calculation amount.

According to “FPGA implementation of MMSE metric based efficient near-MLdetection”, International ITG Workshop on Smart Antennas 2008, 2008-02,pp. 139-146, by M. Joham, L. G. Barbero, T. Lang, W. Utschick, J.Thompson, T. Ratnarajah, in order to obtain performance close to the MLdetection, N paths having a short distance among M path metrics used incalculation of QRD-M are selected using ‘Merge-Sort’. This scheme is ascheme of sorting M path metrics and selecting N path metrics having aminimum value among the M path metrics.

According to the conventional QRD-M, all of M metrics are first sortedwhen N metrics are selected among the M metrics.

FIG. 1 shows a Merge-Sort process of calculating 3 metrics among 8metrics. FIG. 2 shows Merge-Sort 4, 8, and 16 values.

Since 8 metrics are present, they may be represented by a distance of 4bits. As shown in FIG. 2, since each of Merge-Sort 4, 8, and 16 valuespasses through a critical path of two, three, and four comparators, aMerge-Sort process of calculating 3 minimum values among 8 distancevalues of 4 bits has a critical path passing through 6 comparators.

FIG. 3 shows a logic calculating 64 minimum values among 256 distancevalues. It is shown that 36 critical paths passes through 3839comparators in order to calculate 64 minimum values among 256 distancevalues

FIG. 4 shows a process of calculating 1 minimum value among 8 distancevalues of 4 bits. This shows a critical path passing through 3comparators.

In the conventional algorithm as described above, N values are selectedafter passing through complicated sorting.

Hereinafter, according to the present invention, a method of calculatingN minimum values by sequentially searching the most significant bit(MSB) to the least significant bit (LSB) from M metrics without passingthrough a sorting algorithm is suggested.

Consider a case in which N metrics having a small size are selectedamong M metrics P(i) (i=1, 2, . . . , M) represented by B bits.P(i)=[b_(i)(B−1) . . . b_(i)(1) b_(i)(0)].

The sum (sum(j)) of the j-th bits of M P(i)s is represented by thefollowing Equation.

$\begin{matrix}{{{sum}(j)} = {\sum\limits_{i = 1}^{M}{b_{i}(j)}}} & \left\lbrack {{Equation}\mspace{14mu} 7} \right\rbrack\end{matrix}$

First, consider a case in which B=1.

P(i)=[b_(i)(0)]. The sum of the first bits of M P(i)s is represented bythe following Equation.

$\begin{matrix}{{{sum}(0)} = {\sum\limits_{i = 1}^{M}{b_{i}(0)}}} & \left\lbrack {{Equation}\mspace{14mu} 8} \right\rbrack\end{matrix}$

When sum(0) is larger than (M−N), bits of which M-sum(0) b_(i)(0) bitvalue is 0 are selected, and bits of which N−(M-sum(0)) b_(i)(0) bitvalue is 1 are then arbitrarily selected.

When sum(0) is smaller than (M−N), N metrics are arbitrarily selectedamong things in which M-sum(0) b_(i)(0) bit values are 0.

When sum(0) is the same as (M−N), things in which N b_(i)(0) bit valuesare 0 are selected.

Next, consider a case in which B=2.

P(i)=[b_(i)(1) b_(i)(0)] is initialized to a bit P(i)⁰=0, which meansthat it is selected as minimum values, and is initialized to a bitP(i)¹=0, which means that it is selected as maximum values.

The sum, sum(1), of the second bits of M P(i)s is represented by thefollowing Equation.

$\begin{matrix}{{{sum}(1)} = {\sum\limits_{i = 1}^{M}{b_{i}(1)}}} & \left\lbrack {{Equation}\mspace{14mu} 9} \right\rbrack\end{matrix}$

When sum(1) is larger than (M−N), with respect to i in which M-sum(1)b_(i)(1) bits are 0, P(i)⁰ is set to 1. When sum(1) is smaller than(M−N), with respect to i in which sum(1)b_(i)(1) bits are 1, P(i)¹ isset to 1. When sum(1) is the same as (M−N), with respect to i in whichsum(1) b_(i)(1) bits are 0, P(i)⁰ is set to 1, and with respect to i inwhich sum(1) b_(i)(1) bits are 1, P(i)¹ is set to 1. With respect to anyP(i), a case in which P(i)⁰ and P(i)¹ are simultaneously 1 may notoccur.

When the sum (sum(0)) of the first bits of M P(i)s is calculated, theP(i)selected as a minimum value in advance in previous calculation ofthe second bits allows an effect that b_(i)(0)=0 regardless of theb_(i)(0) value to be generated, and the P(i)selected as a maximum valuein advance in the previous calculation of the second bits allows aneffect that b_(i)(0)=1 regardless of the b_(i)(0) value to be generated.

Since P(i)s not selected in the calculation of the second bitscorresponds to a case in which all of the second bits are 0 (that is,sum(1)<(M−N)) or a case in which all of the second bits are 1 (that is,sum(1)>(M−N)), an effect of the b_(i)(0) value is reflected as it is.Since a case in which P(i)⁰ and P(i)¹ are simultaneously 1 may notoccur, when calculation changed into the following Equation isperformed, all of the above-mentioned contents are included:

$\begin{matrix}{{{sum}(0)} = {{{\sum\limits_{i = 1}^{M}\left( {\sim{P(i)}^{0}} \right)}\&}\mspace{14mu} \left( {P(i)}^{1} \middle| {b_{i}(0)} \right)}} & \left\lbrack {{Equation}\mspace{14mu} 10} \right\rbrack\end{matrix}$

where ‘˜’ indicates an inversion of a bit, ‘&’ indicates an ANDoperation, and ‘|’ indicates an OR operation.

The sum of the first bits in consideration of both of P(i)⁰ and P(i)¹ ofthe M P(i)s is sum(0) of Equation 10.

When sum(0) is larger than (M−N), with respect to i in which M-sum(0))(˜P(i)⁰)&(P(i)¹|b_(i)(0)) bits are 0, P(i)⁰ is set to 1. P(i)s havingP(i)⁰ of 1 are first selected as minimum values, and remaining minimumvalues are arbitrarily selected among P(i)s having P(i)⁰ of 0 and P(i)¹of 0.

When sum(0) is smaller than (M−N), with respect to i in which sum(0)(˜P(i)⁰)&(P(i)¹|b_(i)(0)) bits are 1, P(i)¹ is set to 1. P(i)s havingP(i)⁰ of 1 are first selected as minimum values, and remaining minimumvalues are arbitrarily selected among P(i)s having which P(i)⁰ of 0 andP(i)¹ of 0.

When sum(0) is the same as (M−N), with respect to i in which N)(˜P(i)⁰)&(P(i)¹|b_(i)(0)) bits are 1, P(i)¹ is set to 1. P(i)s havingP(i)⁰ of 1 are selected as minimum values.

P(i)s having P(i)⁰ set to 1 in the previous sum(1) calculation ismaintained as P(i)⁰=1 since)(˜P(i)⁰)&(P(i)¹|b_(i)(0))=0 regardless ofb_(i)(0), and P(i)s having P(i)¹ set to 1 in the previous sum(1)calculation is maintained as P(i)¹=1 since)(˜P(i)⁰)&(P(i)¹|b_(i)(0))=1regardless of b_(i)(0). Therefore, only in the case in which P(i)⁰ andP(i)¹ are simultaneously 0, P(i)⁰ or P(i)¹ is additionally set to 1 oris continuously maintained as 0.

With respect to any P(i), a case in which P(i)⁰ and P(i)¹ aresimultaneously 1 may not occur.

Hereinafter, a case in which P(i) is B bits is generalized anddescribed.

In the case in which P(i) is B bits, it may be represented by thefollowing pseudo-code.

---------- start ---------- for (i=0; i<M; i++) { P(i)⁰=0 and P(i)¹=0 }for(i=B−1; i≧0; i--) { sum = 0 for(j=0; j<M; j++) { sum = sum +(~P(j)⁰)&(P(j)¹ |b_(j)(i)) } if(sum > M−N) { for(j=0; j<M; j++) {if((~P(j)⁰&(P(j)¹ | b_(j)(i))==0) P(j)⁰=1 } } else if(sum < M−N) {for(j=0; j<M; j++) {if((~P(j)⁰&(P(j)¹ | b_(j)(i))==1) P(j)¹=1 } } else {for(j=0; j<M; j++) { if((~P(j)⁰)&(P(j)¹ | b_(j)(i))==0) P(j)⁰=1 elseP(j)¹=1 } } } min = 0; for (i=0; i<M; i++) { if(P(j)⁰==1) { Choose P(i)and min = min + 1 } } for(i=0; i<M; i++) { if(P(j)⁰==0 and P(j)¹==0) {if(min < N) { Choose P(i) and min = min+1 } else { exit } } } for(i=0;i<M; i++) { if(P(j)¹==1) { if(min < N) { Choose P(i) and min = min+1 }else { exit } } } ---------- end ----------

The fact that the above algorithm is valid may be proved through thefollowing process.

(1) in the case in which B=1

(1-1) in the case in which the number of 0s among M is less than N

sum(0) is larger than (M−N), such that P(i) having b_(i)(0) of 0 becomesP(j)⁰=1 to be selected as a minimum value, and remaining minimum valuesare selected among things in which b_(i)(0) having P(j)⁰ of 0 and P(j)¹of 0 is 1. Therefore, the algorithm is valid.

(1-2) in the case in which the number of 0s among M exceeds N

sum(0) is smaller than (M−N), such that P(i) having b_(i)(0) of 1becomes P(j)¹=1 to be not selected as a minimum value, and minimumvalues are selected among things in which b_(i)(0) having P(j)⁰ of 0 andP(j)¹ of 0 is 0. Therefore, the algorithm is valid.

(1-3) in the case in which the number of 0s among M is N

sum(0) is equal to (M−N), such that P(i) having b_(i)(0) of 0 becomesP(i)⁰=1 to be selected as a minimum value. Therefore, the algorithm isvalid.

(2) in the case in which B=k

In the case in which B=K, when it is assumed that extraction of nminimum values among m is valid by the above algorithm, in the case inwhich B=k+1, it is required to prove that the following case is valid.

(2-1) in the case in which the number of MSB 0s among M is less than N

sum(k) is larger than (M−N), such that P(i) having b_(i)(k) of 0 becomesP(i)⁰=1. After selecting these values as minimum values, the abovealgorithm of selecting n=N−(M-sum(k)) minimum values among m=sum(k) hasonly to be performed.

A)(˜P(i)⁰)&(P(i)¹|b_(i)(j)) value is always 0 regardless a b_(i)(j)value during k>j>0.

(2-2) in the case in which the number of MSBs among M exceeds N

sum(k) is smaller than (M−N), such that P(i) having b_(i)(k) of 1becomes P(i)¹=1. After selecting these values as minimum values, theabove algorithm of selecting n=N minimum values among m=M-sum(k) hasonly to be performed.

A)(˜P(i)⁰)&(P(i)¹|b_(i)(j)) value is always 1 regardless a b_(i)(j)value during k>j≧1.

(2-3) in the case in which the number of MSBs among M is N

sum(k) is equal to (M−N), P(i) having b_(i)(k) of 0 becomes P(i)⁰=1, andP(i) having b_(i)(k) of 1 becomes P(i)¹=1. After selecting these valuesas minimum values and maximum values, the above algorithm of selectingn=0 minimum values among m=0 has only to be performed.

FIG. 5 shows a process of calculating 3 minimum values among 8 distancevalues of 4 bits according to an exemplary embodiment of the presentinvention.

An upper bit indicates P(i)¹ and a lower bit indicates P(i)⁰.

During an initializing process, P(i)¹ and P(i)⁰ are set to 0. In thecase of satisfying a condition that sum ≦5, when the j-th bit satisfiesa condition that) (˜P(i)⁰)&(P(i)¹|b_(i)(j))=1, P(i)¹ is set to 1. In thecase of satisfying a condition that sum ≦5, when the j-th bit satisfiesa condition that)(˜P(i)⁰&(P(i)¹|b_(i)(j))=1, P(i)⁰ is set to 0.

As seen in FIG. 5, when each of P(i)¹ and P(i)⁰ is set to 1 once, avalue thereof is not changed to the end, and a case in which P(i)¹ andP(i)⁰ are simultaneously 1 does not occur.

FIG. 6 is a circuit diagram showing a process of calculating 3 minimumvalues among 8 distance values of 4 bits.

A portion indicated by a dotted box in FIG. 6 is a basic block. Thecircuit diagram of FIG. 6 has a structure in which m basic blocks arerepeated. When M increases, the number of rows increases, and when Bincrease, the number of columns increases.

When the suggested algorithm is applied, N=2^(n) minimum values selectedamong M values are indicated by a flag 1 and are disposed and searchedamong the M values. Therefore, there is a need to gather and re-sort theselected minimum values.

FIG. 7 shows a method of sorting selected minimum values. This uses ashift register.

In order to allow N minimum values to remain, M−N+1 clocks are required.In this case, N(B+1) multiplexer and N−1 2-input AND gates are required.In the re-sort scheme as described above, the N minimum values are notsequentially sorted unlike a Merge Sort scheme.

FIG. 8 shows a method of re-sorting 3 minimum values selected among 16values.

After a method of allowing 3 minimum values among 8 values to remain isperformed twice, a method of re-sort 3 minimum values among the 6minimum values is performed to reduce the number of clocks.

In the case of using the method of FIG. 7, 14 clocks are required.However, the same work may be performed using 9 clocks.

When the suggested scheme is applied to a case in which N=1, a method ofcalculating a minimum value among M is obtained.

FIG. 9 is a circuit diagram showing a method of calculating a minimumvalue among 8 distance values of 4 bits. A portion represented by ablack dotted line in FIG. 9 is a basic block. The circuit diagram ofFIG. 9 has a structure in which basic blocks are repeated. When Mincreases, the number of rows increases, and when B increases, thenumber of columns increases.

Checking whether sum ≦M−1 becomes the same as performing an ANDoperation of M bits, and it is not required to check whether sum ≧M−1,such that a circuit configuration becomes simple.

FIG. 10 show a process of calculating a minimum value among 8 distancevalues of 4 bits.

A red bit indicates P(i)¹. During an initializing process, P(i)¹ is setto 0. A condition that sum ≦7, that is, whether or not all(P(i)¹|b_(i)(j)) are 1 is determined by an AND gate. In the case ofsatisfying the condition, P(i)¹ is set to 1. Also in this case, wheneach of P(i)¹ is set to 1 once, a value thereof is not changed to theend.

Hereinafter, the number of comparators and a critical path of theMerge-Sort method of calculating 64 minimum values among 256 distancevalues are compared with those of the suggested scheme to comparecomplexities with each other.

Assume that each metric is B bits. According to the suggested method, acritical path performs 256 1-bit additions B times.

FIG. 11 shows 32 1-bit additions. When it is assumed that 256 1-bitadditions are implemented by being extended to the method as shown inFIG. 11, 128 1-bit additions, 64 2-bit additions, 32 3-bit additions, 164-bit additions, 8 5-bit additions, 4 6-bit additions, 2 7-bitadditions, and 1 8-bit addition are required.

In order to approximately compare complexities with each other, in thecase of using a metric of B=2^(b) bits, the number of gates and acritical path required to design a circuit using a 2-input NAND gate arecalculated. Assume that a comparator of the Merge-Sort method isimplemented using a ripple carry subtractor of B bits. Each comparatorand multiplexer may be implemented by 10B+16B 2-input gates. Thecritical path passes through 7B+5 NAND gates. In order to furtherincrease a speed, the comparator may be implemented by the followingEquation:

X>Y:X _(B-1) Y _(B-1) +a _(B-1) X _(B-2) Y _(B-2) +a _(B-l) a _(B-2) X_(B-3) Y _(B-3) + . . . +a _(B-1) a _(B-2) . . . a ₁ X ₀ Y ₀  [Equation11]

where a_(i)=X_(i)Y_(i)+ X _(i) Y _(i).

In this case, each comparator and multiplexer may be implemented by19B−9+16B 2-input NAND gates, and the critical path passes through2B+2b+5 NAND gates.

The complexity of the Merge-Sort of sorting M=2^(m) values may becalculated by calculating the number of comparators in the scheme ascalculated in FIG. 3.

The complexity at the time of using the suggested algorithm may becalculated as follows.

When M=2^(m) 1-bit additions are calculated by a method as shown in FIG.11, 2^(m+1)−m−1 1-bit full adders are required. When it is assumed thatthe comparator is implemented using a ripple carrier subtractor of mbits and remaining gates are considered using FIG. 6, the comparator maybe implemented by (2^(m+1)−m−1+10 m+17×2^(m))B 2-input NADN gates. Thecritical path passes through (3m(m+1)+7 m+6)B NAND gates.

The complexities of the Merge-Sort scheme and the suggested inventionthrough the above-mentioned method are shown in Table 1.

TABLE 1 Merge-Sort 1 Merge-Sort 2 Suggested Invention Critical CriticalCritical M = 2^(m) B = 2^(b) Complexity Path Complexity Path ComplexityPath 16 8 209,664 610 273,168 270 2,712 752 16 419,328 1,170 555,408 4505,424 1,504 64 8 451,776 1,281 588,612 567 10,152 1,392 16 903,552 2,4571,196,772 945 20,304 2,784 256 8 798,512 2,196 1,040,369 972 39,4802,224 16 1,597,024 4,212 2,115,289 1,620 78,960 4,448

It is appreciated that when the suggested scheme is used, a length ofthe critical path slightly increases; however, the complexitysignificantly decreases. This advantage is more prominent when a size ofM is small.

Table 2 shows results of calculating the complexity for applying there-sort scheme suggested in FIG. 7 using the number of NAND gates.

TABLE 2 Number of Minimum Value N = 4 N = 16 N = 64 Distance Bit B = 8 B= 16 B = 32 B = 8 B = 16 B = 32 B = 8 B = 16 B = 32 Number of 294 5501,062 1,182 2,206 4,254 4,734 8,830 17,022 NAND Gate

The complexities of the suggested method of calculating a minimum valueand a method of using a comparator are compared with each other.

Consider a case of calculating a minimum value among M=2^(m) distancevalues. When it is assumed that the comparator is implemented using aripple carry subtractor, each comparator and multiplexer may beimplemented by 10B+8B 2-input NAND gates. The critical path passesthrough 7B+5 NAND gates. The number of all comparators is M−1, and thenumber of comparators of the critical path is m.

According to the suggested invention, in order to perform an ANDoperation on M bits, M−1 2-input AND gates are required for each bit,and it is necessary to invert an output 1 bit. When remaining circuitelements of FIG. 9 are calculated using the number of NAND gates, theentire complexity may be implemented by B(2M−1+8M) 2-input NAND gates,and the critical path passes through (2m+5)B NAND gates.

The complexities of the method of calculating a minimum value using acomparator and the suggested invention are shown in Table 3.

TABLE 3 Suggested Method of Using Invention Comparator Critical M =2^(m) B = 2^(b) Complexity Critical Path Complexity Path 16 8 2,160 2441,272 104 16 4,320 468 2,544 208 64 8 9,072 366 5,112 136 16 18,144 70210,224 272 256 8 36,720 488 20,472 168 16 73,440 936 40,944 336

As compared to the method of using a comparator, the complexity of thesuggested invention decreases by about a half, and the length of thecritical path also decreases by a half or more. This difference is moreprominent when a size of M is small.

As compared to the result of Table 1 of calculating N minimum values,the complexity decreases by about a half, and the addition is replacedby the AND gate, such that the length of the critical path decreases bya half or more.

FIG. 12 is a block diagram showing a receiver implementing a suggestedembodiment.

The receiver 500 includes a receive circuit 520, a channel estimatingunit 530, a metric determining unit 540, and a restoring unit 550.

The receive circuit 520 receives receive signals from a transmitterthrough a receive antenna 510.

The channel estimating unit 530 estimate channels between the receiver500 and the transmitter.

The metric determining unit 540 determines M metrics (P(i)) representedby B bits based on the channel on which the receive signal is receivedand selects N metrics having a small size among the M metric. Thesuggested function and method may be implemented by the metricdetermining unit 540. The metric determining unit 540 may initialize twocomparison values (P(i)⁰ and P(i)¹) to 0 for each of the M metrics,calculate

the sum

$\left( {{{{sum}(j)} = {{{\sum\limits_{i = 1}^{M}\left( {\sim{P(i)}^{0}} \right)}\&}\mspace{14mu} \left( {P(i)}^{1} \middle| {b_{i}(j)} \right)}},} \right.$

where j=0, 1, . . . , B−1) for each bit of the M metrics, compare thesum (sum(j)) of the j-th bits with (M−N) to determine P(i)⁰ and P(i)¹for each of the M metrics, and select at least one P(i) having a P(i)⁰value of 1.

The restoring unit 550 restores a transmit signal transmitted by thetransmitter from the receive signal based on the N metrics.

The complexity for configuring the circuit may be reduced, and thelength of the critical path may be reduced.

Embodiments of the present invention may be provided on a computerreadable medium. Examples of computer readable media include RandomAccess Memory (RAM), flash memory, Erasable Programmable Read OnlyMemory (EPROM), or other forms of semiconductor memory, a computer harddrive such as a magnetic or solid-state hard drive, optical media suchas a Compact Disc Read-only Memory (CD-ROM), a magnetic storage device,etc. The computer readable medium may include a computer executableprogram thereon, the computer readable medium comprising code forperforming steps in accordance with methods described above.

In view of the exemplary systems described herein, methodologies thatmay be implemented in accordance with the disclosed subject matter havebeen described with reference to several flow diagrams. While forpurposes of simplicity, the methodologies are shown and described as aseries of steps or blocks, it is to be understood and appreciated thatthe claimed subject matter is not limited by the order of the steps orblocks, as some steps may occur in different orders or concurrently withother steps from what is depicted and described herein. Moreover, oneskilled in the art would understand that the steps illustrated in theflow diagram are not exclusive and other steps may be included or one ormore of the steps in the example flow diagram may be deleted withoutaffecting the scope and spirit of the present disclosure.

1. A method of selecting N metrics among M metrics, where M>N≧1, themethod comprising: determining M metrics P(i)=[b_(i)(B−1) . . . b_(i)(1)b_(i)(0)], where i=1, . . . , M, each P(i) being represented by B bits;initializing two comparison values, P(i)⁰ and P(i)¹, to zero for eachP(i); determining a sum of j-th bit for M P(i)s, where j=0, 1, . . . ,B−1, as shown:${{sum}(j)} = {{{\sum\limits_{i = 1}^{M}\left( {\sim{P(i)}^{0}} \right)}\&}\mspace{14mu} \left( {P(i)}^{1} \middle| {b_{i}(j)} \right)}$where sum(j) denotes the sum of j-th bit for M P(i)s, ‘˜’ denotes a bitinversion operation, ‘&’ denotes a bit AND operation, and ‘|’ denotes abit OR operation; updating P(i)⁰ and P(i)¹ for each P(i) by comparingsum(j) and (M−N); and selecting at least one P(i) having a P(i)⁰ valueof 1 among M P(i)s.
 2. The method of claim 1, further comprising:selecting at least one P(i) having a P(i)⁰ value of 1 and a P(i)¹ valueof 0 when the number of selected P(i) is smaller than N.
 3. The methodof claim 2, wherein the step of updating P(i)⁰ and P(i)¹ for each P(i)includes updating P(i)⁰ to 1 with respect to i in which(˜P(i)⁰)&(P(i)¹|b_(i)(j))=0 when sum(j) is larger than (M−N).
 4. Themethod of claim 3, wherein the step of updating P(i)⁰ and P(i)¹ for eachP(i) includes updating P(i)¹ to 1 with respect to i in which(˜P(i)⁰)&(P(i)¹|b_(i)(j))=1 when sum(j) is smaller than (M−N).
 5. Themethod of claim 4, wherein the step of updating P(i)⁰ and P(i)¹ for eachP(i) includes: when sum(j) is the same as (M−N), updating P(i)⁰ to 1with respect to i in which (˜P(i)⁰)&(P(i)¹|b_(i)(j))=0 and updatingP(i)¹ to 1 with respect to i in which (˜P(i)⁰)&(P(i)¹|b_(i)(j))=1.
 6. Amethod of receiving data, the method comprising: receiving a receivesignal from a transmitter; determining M metrics P(i)=[b_(i)(B−1) . . .b_(i)(1) b_(i)(0)], where i=1, . . . , M, based on a channel on whichthe receive signal is received, each P(i) being represented by B bits;determining N metrics among the M P(i)s, where M>N≧1; and restoring atransmit signal transmitted by the transmitter from the receive signalbased on the N metrics, wherein the step of determining N metricsincludes: initializing two comparison values, P(i)⁰ and P(i)¹, to zerofor each P(i); determining a sum of j-th bit for M P(i)s, where j=0, 1,. . . , B−1, as shown:${{sum}(j)} = {{{\sum\limits_{i = 1}^{M}\left( {\sim{P(i)}^{0}} \right)}\&}\mspace{14mu} \left( {P(i)}^{1} \middle| {b_{i}(j)} \right)}$where sum(j) denotes the sum of j-th bit for M P(i)s, ‘˜’ denotes a bitinversion operation, ‘&’ denotes a bit AND operation, and ‘|’ denotes abit OR operation; updating P(i)⁰ and P(i)¹ for each P(i) by comparingsum(j) and (M−N); and selecting at least one P(i) having a P(i)⁰ valueof 1 among M P(i)s.
 7. The method of claim 6, wherein the step ofdetermining N metrics further includes: selecting at least one P(i)having a P(i)⁰ value of 1 and a P(i)¹ value of 0 when the number ofselected P(i) is smaller than N.
 8. The method of claim 7, wherein thestep of updating P(i)⁰ and P(i)¹ for each P(i) includes updating P(i)⁰to 1 with respect to i in which (˜P(i)⁰)&(P(i)¹|b_(i)(j))=0 when sum(j)is larger than (M−N).
 9. The method of claim 8, wherein the step ofupdating P(i)⁰ and P(i)¹ for each P(i) includes updating P(i)¹ to 1 withrespect to i in which (˜P(i)⁰)&(P(i)¹|b_(i)(j))=1 when sum(j) is smallerthan (M−N).
 10. The method of claim 9, wherein the step of updatingP(i)⁰ and P(i)¹ for each P(i) includes: when sum(j) is the same as(M−N), updating P(i)⁰ to 1 with respect to i in which(˜P(i)⁰)&(P(i)¹|b_(i)(j))=0 and updating P(i)¹ to 1 with respect to i inwhich (˜P(i)⁰)&(P(i)¹|b_(i)(j))=1.
 11. A receiver comprising: a receivecircuit configured for receiving a receive signal from a transmitter; ametric determining unit configured for determining M metricsP(i)=[b_(i)(B−1) . . . b_(i)(1) b_(i)(0)], where i=1, . . . , M, basedon a channel on which the receive signal is received, each P(i) beingrepresented by B bits, and determining N metrics among the M P(i)s,where M>N≧1; and a restoring unit configured for restoring a transmitsignal transmitted by the transmitter from the receive signal based onthe N metrics, wherein the metric determining unit is configured fordetermining N metrics by: initializing two comparison values, P(i)⁰ andP(i)¹, to zero for each P(i); determining a sum of j-th bit for M P(i)s,where j=0, 1, . . . , B−1, as shown:${{sum}(j)} = {{{\sum\limits_{i = 1}^{M}\left( {\sim{P(i)}^{0}} \right)}\&}\mspace{14mu} \left( {P(i)}^{1} \middle| {b_{i}(j)} \right)}$where sum(j) denotes the sum of j-th bit for M P(i)s, ‘˜’ denotes a bitinversion operation, ‘&’ denotes a bit AND operation, and ‘|’ denotes abit OR operation; updating P(i)⁰ and P(i)¹ for each P(i) by comparingsum(j) and (M−N); and selecting at least one P(i) having a P(i)⁰ valueof 1 among M P(i)s.
 12. The receiver of claim 11, wherein the metricdetermining unit is configured for determining N metrics by: selectingat least one P(i) having a P(i)⁰ value of 1 and a P(i)¹ value of 0 whenthe number of selected P(i) is smaller than N.
 13. The receiver of claim12, wherein the metric determining unit is configured for updating P(i)⁰and P(i)¹ for each P(i) by: updating P(i)⁰ to 1 with respect to i inwhich (˜P(i)⁰)&(P(i)¹|b_(i)(j))=0 when sum(j) is larger than (M−N). 14.The receiver of claim 13, wherein the metric determining unit isconfigured for updating P(i)⁰ and P(i)¹ for each P(i) by: updating P(i)¹to 1 with respect to i in which (˜P(i)⁰)&(P(i)¹|b_(i)(j))=1 when sum(j)is smaller than (M−N).
 15. The receiver of claim 14, wherein the metricdetermining unit is configured for updating P(i)⁰ and P(i)¹ for eachP(i) by: when sum(j) is the same as (M−N), updating P(i)⁰ to 1 withrespect to i in which) (˜P(i)⁰)&(P(i)¹|b_(i)(j))=0 and updating P(i)¹ to1 with respect to i in which (˜P(i)⁰)&(P(i)¹|b_(i)(j))=1.